The present invention relates to a power metal oxide semiconductor type field effect transistor (hereinafter referred to as MOS FET), and more particularly to an improvement in a characteristic of a diode included in or internal to such a power MOS FET.
Generally, as a large power MOS FET for a large current and/or a high voltage, various types of double diffusion type MOS FETs (abbreviated as D-MOS FETs, which include as their special forms V-MOS FET and U-MOS FET) have been used. In any of the types, a parasitic diode is inherently formed due to the physical construction of the D-MOS FET.
FIG. 1 is a sectional view showing a typical D-MOS FET. In the figure, reference numeral 1 denotes an N.sup.+ type high concentration silicon substrate, and reference numeral 2 denotes an N.sup.- type low concentration silicon epitaxial layer. A drain region of the MOS FET is formed by both of the layers 1 and 2. Reference numeral 3 denotes a drain electrode. Further, a diffusion region 4 with a P type impurity diffused is formed within the N.sup.- type epitaxial layer 2, and an N.sup.+ type impurity diffused region 5 is formed within the P type impurity diffused region 4, wherein the P type impurity diffused region 4 constitutes a base region for a channel portion while the N.sup.+ impurity diffused region 5 constitutes a source region. Provided above the N.sup.- type epitaxial layer 2 and the channel portion base region is a gate insulator layer 6 extending up to a portion of the surface of the source region 5, and a gate electrode 7 is formed above the gate insulator layer 6. Further, an interlayer insulator layer 8 and a source electrode layer 9 are formed in superposition with each other in the stated order on the gate electrode 7. The source electrode layer 9 is connected to the source region 5 and the base region 4 as well. The above-mentioned V-MOS FETs and U-MOS FETs have principally the same construction, although they differ in form.
An equivalent circuit for the power MOS FET constructed as above is shown in FIG. 2. In FIG. 2, a drain electrode D corresponds to the N.sup.+ type silicon substrate 1 and the N.sup.- type epitaxial layer 2, a source electrode S corresponds to the N.sup.+ type impurity diffused region 5, and a gate electrode G corresponds to the gate electrode 7, respectively in FIG. 1. The diode D1 shown in FIG. 2 is formed parasitically, the P type impurity diffused region 4 of FIG. 1 serving as an anode and the N.sup.- type epitaxial layer 2 serving as a cathode.
As described above, the power MOS FET includes a parasitic diode, so that when the FET is used in an inverter circuit for motor control, the parasitic diode can be utilized as a flywheel diode, with the result that separate flywheel diodes which had to be connected outside of the FET can be dispensed with, and hence the number of parts can be reduced. It has therefore been said that the power MOS FET has, in addition to the advantages such as a high switching speed, a high efficiency, a broad safely operating region, and a high resistance against breakage, a capability of reducing the number of parts and hence the cost.
However, it has been found that when such power MOS FETs are actually utilized in an inverter circuit shown in part in FIG. 3 for controlling a motor, the parasitic diode has a long reverse recovery time (t.sub.rr) and a large power loss so that it cannot be used as a flywheel diode. The following is a detailed description on this point.
FIG. 3 shows a portion of an inverter circuit, in which two MOS FETs 1 and 2 are serially connected to each other, and a motor winding L is connected to the node connecting the MOS FETs 1 and 2. Control signals are input to the gates G1 and G2 of the MOS FETs 1 and 2 to control the conductions of the MOS FETs 1 and 2, and thus the winding L is excited to control the rotation of the motor.
When the MOS FET 2 is nonconductive, the load current I.sub.L flows as a flywheel current I.sub.D1 passing through the internal diode D.sub.1. However, when the MOS FET 2 is subsequently turned on, a current I.sub.T flows through the MOS FET 2 which is the sum of the load current I.sub.L and a reverse recovery current I.sub.D from the internal diode D.sub.1. The load current I.sub.L, flywheel current I.sub.D1 of the internal diode D.sub.1, current I.sub.T (=I.sub.L +I.sub.D1) passing through the MOS FET 2, and the voltage V.sub.T applied to the MOS FET 2 vary with time as shown in FIG. 4. A hatched portion in the current I.sub.D1 represents the reverse recovery current I.sub.D, and the current I.sub.T flowing then is the sum of the on-time current I.sub.L and the current I.sub.D.
As seen from FIG. 4, the reverse recovery current I.sub.D is very large, resulting in a large power loss in the MOS FET 2. The power loss becomes larger, with longer reverse recovery time (T.sub.rr(1)) of the internal diode D.sub.1, and the MOS FET 2 may therefore break down.